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A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.

A. Raychowdhury, S. Ghosh, S. Bhunia, D. Ghosh, and K. Roy. ETS, page 108-113. IEEE Computer Society, (2005)

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Asamanjoy Bhunia

Anirban Bhunia

Krishna Swarup Jauhri

Other publications of authors with the same name

Eat, but Verify: Low-Cost Portable Devices for Food Safety Analysis.N. Masna, S. Paul, C. Chen, S. Mandal, and S. Bhunia. IEEE Consumer Electronics Magazine, 8 (1): 12-18 (2019)Resilient System-on-Chip Designs With NoC Fabrics.A. Nath, S. Boddupalli, S. Bhunia, and S. Ray. IEEE Trans. Inf. Forensics Secur., (2020)An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools.W. Hu, C. Chang, A. Sengupta, S. Bhunia, R. Kastner, and H. Li. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (6): 1010-1038 (2021)Third-Party Hardware IP Assurance against Trojans through Supervised Learning and Post-processing.P. Gaikwad, J. Cruz, P. Chakraborty, S. Bhunia, and T. Hoque. CoRR, (2021)Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm TechnologiesA. Datta, S. Bhunia, S. Mukhopadhyay, N. Banerjee, and K. Roy. CoRR, (2007)ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric (Abstact Only).W. Qian, C. Babecki, R. Karam, and S. Bhunia. FPGA, page 275. ACM, (2016)Internet of Things security: Are we paranoid enough?S. Bhunia. ICCE, page 1. IEEE, (2018)Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic CircuitsS. Mukhopadhyay, S. Bhunia, and K. Roy. CoRR, (2007)On-Chip Batteries as Distributed Energy Sources in Heterogeneous 2.5D/3D Integrated Circuits.P. Dehghanzadeh, J. Huan, R. Kalavakonda, S. Mandal, and S. Bhunia. IEEE Access, (2023)IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering Attacks.C. Vega, P. SLPSK, and S. Bhunia. IEEE Trans. Very Large Scale Integr. Syst., 32 (2): 347-360 (February 2024)

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Disambiguation of "Bhunia, Swarup"

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A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.

Please choose a person to relate this publication to

Asamanjoy Bhunia

Anirban Bhunia

Krishna Swarup Jauhri

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Bhunia, Swarup"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.

Please choose a person to relate this publication to

Asamanjoy Bhunia

Anirban Bhunia

Krishna Swarup Jauhri

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.