Review on Designing of Multi Bit Flip-Flop to Achieve Reduced Area in VLSI Design
International Journal of Innovative Science and Modern Engineering (IJISME), 3 (9):
1-2 (August 2015)Abstract
In this paper, we have designed Multi-bit Flip-flop (MBFF) and made performance comparison over the Single-bit Flip-flop (SBFF) We can increase Flip flop performance by merging clock pulse. But increase in clock pulse means it will increases the area. So the Multi-bit Flip-flop is designed by single clock pulse and achieves same functionality like two single-bit Flip-flop so it will reduce the area. The basic memory elements of designer considerations are Latch and flip flop. Optimizations in VLSI have been done on three factors: Area, Power and Timing (Speed). Area optimization means reducing the space of logic which occupy on the die. Memory elements play a vital role on Digital World but these elements consumes more area. Thus these elements can be designed using Multi-bit flip flop to reduce area.